1. Field of the invention
The present invention generally relates to a nonvolatile memory and method of forming the same, and more particularly, the present invention relates to a flash memory and a method of forming the same.
This application is a counterpart of Japanese application Ser. No. 074715/1998, filed Mar. 23, 1998, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 1 is a cross sectional view showing a conventional flash memory cell. As shown in FIG. 1, the conventional flash memory cell includes a stacked layer structure which comprises a control gate electrode 6, an insulating film 5, a floating gate electrode 4, and a tunnel oxide film 3 on a p type semiconductor substrate 10 having an n.sup.+ type source region 1, an n.sup.+ type source region 7, an n.sup.+ type drain region 2, a p.sup.+ type drain region 8. The flash memory cell has a structure which is similar to that of an EPROM (Erasable Programmable Read Only Memory). However, in the conventional flash memory cell, the tunnel oxide film 3, having a thickness of about 10 nm, is formed instead of a gate oxide film as in an EPROM. The n.sup.+ type source region 7 is formed under the n.sup.+ type source region 1 to prevent a tunnel leakage between bands. On the other hand, the p.sup.+ type drain region 8 is formed under the n.sup.+ type drain region 2 to achieve programming efficiency.
The program (write) operation is performed by injecting electrons from the n.sup.+ type drain region 2 to the floating gate electrode 4. Therefore, when predetermined voltages, for example 10V, 5V, 0V, are applied to the control gate electrode 6, the n.sup.+ type drain region 2, and the n.sup.+ type source region 1, hot electrons occur near the n.sup.+ type drain region 2, and as a result the hot electrons are injected into the floating gate electrode 4. Therefore, the memory cell becomes the condition ("0") that a threshold voltage is a high.
On the other hand, the erase operation is performed by emitting the electrons in the floating gate electrode 4 into the n.sup.+ type source region 1 via the tunnel oxide film 3. FIG. 2 is a schematic energy band diagram of a conventional flash memory cell in the erase operation. As shown in FIG. 2, the erase operation is performed by applying a high voltage to the tunnel oxide film 3, emitting the electrons stored in the floating gate electrode 4 by tunneling, and forming the condition ("1") that a threshold voltage is low. More specifically, the erase operation is performed by applying -10V and 5V to the control gate electrode 6 and the n.sup.+ type source region 1, respectively, while opening the n.sup.+ type drain region 2.
Further, the read operation is performed as follows. By respectively applying 1V, 5V and 0V to the control gate electrode 6, the n.sup.+ type drain region 2, and the n.sup.+ type source region 1, a memory cell is selected, as a result the condition of the threshold voltage of the memory cell is detected.
The conventional flash memory has disclosed in "Semiconductor World, April 1991, pp. 94-98".
In the conventional nonvolatile memory, it is desirable to prevent a situation in which the number of program and erasure cycles is decreased by a degradation of the tunnel oxide film.